1. Technical Field
The present invention relates generally to semiconductor fabrication and more particularly to self-aligned dual stressed layers for enhancing both n-type and p-type field effect transistors.
2. Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents). One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride layers. For example, a tensile-stressed silicon nitride layer may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride layer may be used to cause compression in a PFET channel. Accordingly, a dual stressed barrier layer is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of a dual barrier silicon nitride layers for stress enhancement of NFET/PFET devices, the first deposited layer is deposited and then is removed over the appropriate FET region by patterning and etching. The second layer is then deposited and then removed over the other of the two FET regions by patterning and etching. Due to misalignment of lithography and etching, either overlap or underlap may occur in the place where tensile and compressive layers meet after etching the second layer. The overlap and underlap can appear on/above the surface of underlying silicide. In particular, in cases where the layers do not meet (i.e., underlap), exposure of underlying materials can be problematic. For example, overetching of the underlying material typically results where underlap is present. In another example, where the underlying material is silicide, both overetching and oxidization of the silicide become issues. Alternatively, where the layers overlap, the increased thickness creates other problems. For example, etching via openings through the dual layer takes longer than in other locations where only one of the layers is present. As a result, over etching of areas where the overlap does not occur result in, for example, an increasing of the resistance of the silicide (or even a broken silicide line if the over etched area is on the top of gate conductor) or increasing junction leakage due to over-etching into the junction area in device source/drain and extension regions. Accordingly, one challenge relative to using compressive and tensile layers is achieving an alignment between the layers where they meet.
In view of the foregoing, there is a need in the art for self-aligned dual stressed layers.